From 2893ca09d5f8cf6163e70773cefb3f698e21ca0a Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Thu, 25 Jul 2024 14:13:30 +0300 Subject: [PATCH 1/6] Audio: MFCC: Fix build of component for current SOF It has not been possible to build the component earlier for Zephyr IPC4 systems. This patch makes the next fixes: - Add SOF_MODULE_INIT() and include of rtos/init.h - For unit test fix the init function to sys_comp_module_mfcc_interface_init() - To Zephyr/CMakeLists.txt add the needed math library sources - Add .toml files for rimage for IPC4 systems Signed-off-by: Seppo Ingalsuo --- src/audio/mfcc/mfcc.c | 2 + src/audio/mfcc/mfcc.toml | 21 ++++++++++ src/include/sof/audio/mfcc/mfcc_comp.h | 5 +-- tools/rimage/config/tgl-h.toml | 18 ++++++++- tools/rimage/config/tgl.toml | 18 ++++++++- zephyr/CMakeLists.txt | 55 ++++++++++++++++++++++++++ 6 files changed, 113 insertions(+), 6 deletions(-) create mode 100644 src/audio/mfcc/mfcc.toml diff --git a/src/audio/mfcc/mfcc.c b/src/audio/mfcc/mfcc.c index ab609ce66cd4..7adb33839389 100644 --- a/src/audio/mfcc/mfcc.c +++ b/src/audio/mfcc/mfcc.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -257,3 +258,4 @@ static const struct module_interface mfcc_interface = { }; DECLARE_MODULE_ADAPTER(mfcc_interface, mfcc_uuid, mfcc_tr); +SOF_MODULE_INIT(mfcc, sys_comp_module_mfcc_interface_init); diff --git a/src/audio/mfcc/mfcc.toml b/src/audio/mfcc/mfcc.toml new file mode 100644 index 000000000000..5b07b2377752 --- /dev/null +++ b/src/audio/mfcc/mfcc.toml @@ -0,0 +1,21 @@ +#ifndef LOAD_TYPE +#define LOAD_TYPE "0" +#endif + +REM # MFCC module config +[[module.entry]] +name = "MFCC" +uuid = "DB10A773-1AA4-4CEA-A21F-2D57A5C982EB" +affinity_mask = "0x1" +instance_count = "40" +domain_types = "0" +load_type = LOAD_TYPE +module_type = "9" +auto_start = "0" +sched_caps = [1, 0x00008000] +REM # pin = [dir, type, sample rate, size, container, channel-cfg] +pin = [0, 0, 0xfeef, 0xf, 0xf, 0x45ff, 1, 0, 0xfeef, 0xf, 0xf, 0x1ff] +REM # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] +mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] + +index = __COUNTER__ diff --git a/src/include/sof/audio/mfcc/mfcc_comp.h b/src/include/sof/audio/mfcc/mfcc_comp.h index 6d0f57086b39..ee8d9e5e4bbd 100644 --- a/src/include/sof/audio/mfcc/mfcc_comp.h +++ b/src/include/sof/audio/mfcc/mfcc_comp.h @@ -50,9 +50,6 @@ #endif #define MFCC_NORMALIZE_MAX_SHIFT 10 -struct audio_stream; -struct comp_dev; - /** \brief Type definition for processing function select return value. */ typedef void (*mfcc_func)(struct processing_module *mod, struct input_stream_buffer *bsource, @@ -189,7 +186,7 @@ void mfcc_s16_default(struct processing_module *mod, struct input_stream_buffer #endif #ifdef UNIT_TEST -void sys_comp_mfcc_init(void); +void sys_comp_module_mfcc_interface_init(void); #endif #endif /* __SOF_AUDIO_MFCC_MFCC_COMP_H__ */ diff --git a/tools/rimage/config/tgl-h.toml b/tools/rimage/config/tgl-h.toml index cfdcdd8490bd..6146fb89eef8 100644 --- a/tools/rimage/config/tgl-h.toml +++ b/tools/rimage/config/tgl-h.toml @@ -60,7 +60,7 @@ name = "ADSPFW" load_offset = "0x30000" [module] -count = 24 +count = 25 [[module.entry]] name = "BRNGUP" uuid = "61EB0CB9-34D8-4F59-A21D-04C54C21D3A4" @@ -546,3 +546,19 @@ count = 24 pin = [0, 0, 0xfeef, 0xf, 0xf, 0x45ff, 1, 0, 0xfeef, 0xf, 0xf, 0x1ff] # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] + + # MFCC module config + [[module.entry]] + name = "MFCC" + uuid = "DB10A773-1AA4-4CEA-A21F-2D57A5C982EB" + affinity_mask = "0x1" + instance_count = "40" + domain_types = "0" + load_type = "0" + module_type = "9" + auto_start = "0" + sched_caps = [1, 0x00008000] + # pin = [dir, type, sample rate, size, container, channel-cfg] + pin = [0, 0, 0xfeef, 0xf, 0xf, 0x45ff, 1, 0, 0xfeef, 0xf, 0xf, 0x1ff] + # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] + mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] diff --git a/tools/rimage/config/tgl.toml b/tools/rimage/config/tgl.toml index 9b59c52c1a98..8bd36d4c8da6 100644 --- a/tools/rimage/config/tgl.toml +++ b/tools/rimage/config/tgl.toml @@ -60,7 +60,7 @@ name = "ADSPFW" load_offset = "0x30000" [module] -count = 24 +count = 25 [[module.entry]] name = "BRNGUP" uuid = "61EB0CB9-34D8-4F59-A21D-04C54C21D3A4" @@ -546,3 +546,19 @@ count = 24 pin = [0, 0, 0xfeef, 0xf, 0xf, 0x45ff, 1, 0, 0xfeef, 0xf, 0xf, 0x1ff] # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] + + # MFCC module config + [[module.entry]] + name = "MFCC" + uuid = "DB10A773-1AA4-4CEA-A21F-2D57A5C982EB" + affinity_mask = "0x1" + instance_count = "40" + domain_types = "0" + load_type = "0" + module_type = "9" + auto_start = "0" + sched_caps = [1, 0x00008000] + # pin = [dir, type, sample rate, size, container, channel-cfg] + pin = [0, 0, 0xfeef, 0xf, 0xf, 0x45ff, 1, 0, 0xfeef, 0xf, 0xf, 0x1ff] + # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] + mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 43003dec8529..f9b26ef47363 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -447,6 +447,52 @@ zephyr_library_sources_ifdef(CONFIG_MATH_LUT_SINE_FIXED ${SOF_MATH_PATH}/lut_trig.c ) +zephyr_library_sources_ifdef(CONFIG_MATH_FFT + ${SOF_MATH_PATH}/fft/fft_common.c +) + +zephyr_library_sources_ifdef(CONFIG_MATH_16BIT_FFT + ${SOF_MATH_PATH}/fft/fft_16.c + ${SOF_MATH_PATH}/fft/fft_16_hifi3.c +) + +zephyr_library_sources_ifdef(ONFIG_MATH_32BIT_FFT + ${SOF_MATH_PATH}/fft/fft_32.c + ${SOF_MATH_PATH}/fft/fft_32_hifi3.c +) + +zephyr_library_sources_ifdef(CONFIG_MATH_DCT + ${SOF_MATH_PATH}/dct.c +) + +zephyr_library_sources_ifdef(CONFIG_MATH_WINDOW + ${SOF_MATH_PATH}/window.c +) + +zephyr_library_sources_ifdef(CONFIG_MATH_MATRIX + ${SOF_MATH_PATH}/matrix.c +) + +zephyr_library_sources_ifdef(CONFIG_MATH_AUDITORY + ${SOF_MATH_PATH}/auditory/auditory.c +) + +zephyr_library_sources_ifdef(CONFIG_MATH_16BIT_MEL_FILTERBANK + ${SOF_MATH_PATH}/auditory/mel_filterbank_16.c +) + +zephyr_library_sources_ifdef(CONFIG_MATH_32BIT_MEL_FILTERBANK + ${SOF_MATH_PATH}/auditory/mel_filterbank_32.c +) + +zephyr_library_sources_ifdef(CONFIG_NATURAL_LOGARITHM_FIXED + ${SOF_MATH_PATH}/log_e.c +) + +zephyr_library_sources_ifdef(CONFIG_BINARY_LOGARITHM_FIXED + ${SOF_MATH_PATH}/base2log.c +) + # SOF module interface functions add_subdirectory(../src/module module_unused_install/) @@ -868,6 +914,15 @@ zephyr_library_sources_ifdef(CONFIG_COMP_MUX ${SOF_AUDIO_PATH}/mux/mux_${ipc_suffix}.c ) +zephyr_library_sources_ifdef(CONFIG_COMP_MFCC + ${SOF_AUDIO_PATH}/mfcc/mfcc.c + ${SOF_AUDIO_PATH}/mfcc/mfcc_setup.c + ${SOF_AUDIO_PATH}/mfcc/mfcc_common.c + ${SOF_AUDIO_PATH}/mfcc/mfcc_generic.c + ${SOF_AUDIO_PATH}/mfcc/mfcc_hifi3.c + ${SOF_AUDIO_PATH}/mfcc/mfcc_hifi4.c +) + zephyr_library_sources_ifdef(CONFIG_COMP_GOOGLE_HOTWORD_DETECT ${SOF_AUDIO_PATH}/google/google_hotword_detect.c ) From 88407bfff68bcdcd96f04108427be6a2ad0b9eaf Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Tue, 20 Aug 2024 15:13:53 +0300 Subject: [PATCH 2/6] Tools: Topology2: Move IIR blob define to upper level from pipeline The same dai-copier-eqiir-gain-module-copier-capture pipeline can be used for both DMIC0 and DMIC1, with different IIR setting, so the blob definition is moved to dmic-generic.conf where the pipeline is instantiated. Signed-off-by: Seppo Ingalsuo --- .../cavs/dai-copier-eqiir-gain-module-copier-capture.conf | 8 -------- tools/topology/topology2/platform/intel/dmic-generic.conf | 5 +++++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/tools/topology/topology2/include/pipelines/cavs/dai-copier-eqiir-gain-module-copier-capture.conf b/tools/topology/topology2/include/pipelines/cavs/dai-copier-eqiir-gain-module-copier-capture.conf index 009a632a1d5b..5bd1ad80446e 100644 --- a/tools/topology/topology2/include/pipelines/cavs/dai-copier-eqiir-gain-module-copier-capture.conf +++ b/tools/topology/topology2/include/pipelines/cavs/dai-copier-eqiir-gain-module-copier-capture.conf @@ -109,14 +109,6 @@ Class.Pipeline."dai-copier-eqiir-gain-module-copier-capture" { out_ch_map $CHANNEL_MAP_3_POINT_1 } ] - - Object.Control.bytes."1" { - IncludeByKey.DMIC0_DAI_EQIIR { - "passthrough" "include/components/eqiir/passthrough.conf" - "highpass_40hz_0db" "include/components/eqiir/highpass_40hz_0db_48khz.conf" - "highpass_40hz_20db" "include/components/eqiir/highpass_40hz_20db_48khz.conf" - } - } } gain."1" { diff --git a/tools/topology/topology2/platform/intel/dmic-generic.conf b/tools/topology/topology2/platform/intel/dmic-generic.conf index 29b905cb43a2..d97f2a417f99 100644 --- a/tools/topology/topology2/platform/intel/dmic-generic.conf +++ b/tools/topology/topology2/platform/intel/dmic-generic.conf @@ -285,6 +285,11 @@ IncludeByKey.PASSTHROUGH { Object.Widget.eqiir.1 { Object.Control.bytes."1" { name 'DMIC0 Capture IIR Eq' + IncludeByKey.DMIC0_DAI_EQIIR { + "passthrough" "include/components/eqiir/passthrough.conf" + "highpass_40hz_0db" "include/components/eqiir/highpass_40hz_0db_48khz.conf" + "highpass_40hz_20db" "include/components/eqiir/highpass_40hz_20db_48khz.conf" + } } num_input_audio_formats 1 num_output_audio_formats 1 From 4b211642303c88d495eb3bf9d80ca39be6ee3732 Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Mon, 17 Jun 2024 18:45:50 +0300 Subject: [PATCH 3/6] Tools: Topology2: Add MFCC component and topologies for hda-generic This patch adds build of topologies - sof-hda-generic-cavs25-2ch-mfcc.tplg - sof-hda-generic-cavs25-4ch-mfcc.tplg - sof-hda-generic-ace1-2ch-mfcc.tplg - sof-hda-generic-ace1-4ch-mfcc.tplg The MFCC is connected to 16 kHz DMIC1 DAI. The MFCC bitstream is passed to capture PCM. The DMIC1 pipeline style is copied from DMIC0: DAI copier -> IIR -> gain -> module_copier -> MFCC -> host copier Signed-off-by: Seppo Ingalsuo --- .../topology2/development/tplg-targets.cmake | 22 + .../eqiir/highpass_100hz_0db_16khz.conf | 19 + .../eqiir/highpass_100hz_0db_48khz.conf | 19 + .../eqiir/highpass_100hz_20db_16khz.conf | 19 + .../eqiir/highpass_100hz_20db_48khz.conf | 19 + .../topology2/include/components/mfcc.conf | 64 +++ .../include/components/mfcc/default.conf | 22 + .../platform/intel/dmic-default.conf | 1 + .../platform/intel/dmic-generic.conf | 1 + .../topology2/platform/intel/dmic1-mfcc.conf | 422 ++++++++++++++++++ 10 files changed, 608 insertions(+) create mode 100644 tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_16khz.conf create mode 100644 tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_48khz.conf create mode 100644 tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_16khz.conf create mode 100644 tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_48khz.conf create mode 100644 tools/topology/topology2/include/components/mfcc.conf create mode 100644 tools/topology/topology2/include/components/mfcc/default.conf create mode 100644 tools/topology/topology2/platform/intel/dmic1-mfcc.conf diff --git a/tools/topology/topology2/development/tplg-targets.cmake b/tools/topology/topology2/development/tplg-targets.cmake index dde7ed07b85c..bec343c58c04 100644 --- a/tools/topology/topology2/development/tplg-targets.cmake +++ b/tools/topology/topology2/development/tplg-targets.cmake @@ -234,6 +234,28 @@ PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-tgl-nocodec-crossover.bin,EFX_CROSSOVE "development/cavs-nocodec-rtcaec\;sof-tgl-nocodec-rtcaec\;PLATFORM=tgl,\ PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-tgl-nocodec-rtcaec.bin" +# Add MFCC to 16 kHz DMIC1, 2ch with NHLT - cAVS +"sof-hda-generic\;sof-hda-generic-cavs25-2ch-mfcc\;HDA_CONFIG=mix,\ +PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-hda-generic-cavs25-2ch-mfcc.bin,\ +NUM_DMICS=2,DMIC1_RATE=16000,DMIC1_ENABLE=MFCC,DMIC1_MFCC_PARAMS=default" + +# Add MFCC to 16 kHz DMIC1, 2ch with NHLT - ACE1 +"sof-hda-generic\;sof-hda-generic-ace1-2ch-mfcc\;PLATFORM=mtl,HDA_CONFIG=mix,\ +PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-hda-generic-ace1-2ch-mfcc.bin,\ +NUM_DMICS=2,DMIC1_RATE=16000,DMIC1_ENABLE=MFCC,DMIC1_MFCC_PARAMS=default" + +# Add MFCC to 16 kHz DMIC1, 4ch with NHLT - cAVS +"sof-hda-generic\;sof-hda-generic-cavs25-4ch-mfcc\;HDA_CONFIG=mix,\ +PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-hda-generic-cavs25-4ch-mfcc.bin,\ +NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,DMIC1_RATE=16000,\ +DMIC1_ENABLE=MFCC,DMIC1_MFCC_PARAMS=default" + +# Add MFCC to 16 kHz DMIC1, 4ch with NHLT - ACE1 +"sof-hda-generic\;sof-hda-generic-ace1-4ch-mfcc\;PLATFORM=mtl,HDA_CONFIG=mix,\ +PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-hda-generic-ace1-4ch-mfcc.bin,\ +NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,DMIC1_RATE=16000,\ +DMIC1_ENABLE=MFCC,DMIC1_MFCC_PARAMS=default" + # Topology for SOF plugin "development/sof-plugin\;sof-plugin\;NOISE_SUPPRESSION=false" diff --git a/tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_16khz.conf b/tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_16khz.conf new file mode 100644 index 000000000000..0d9710dbd105 --- /dev/null +++ b/tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_16khz.conf @@ -0,0 +1,19 @@ +# 100 Hz second order high-pass, gain 0 dB, created with sof_example_iir_eq.m 03-Jun-2024 +Object.Base.data."iir_eq" { + bytes " + 0x53,0x4f,0x46,0x34,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x00,0xa0,0x01,0x03, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x02,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xf5,0x18,0x75,0xc3, + 0x6b,0x52,0x72,0x7c,0x6e,0x92,0x32,0x1f, + 0x24,0xdb,0x9a,0xc1,0x6e,0x92,0x32,0x1f, + 0x00,0x00,0x00,0x00,0xb4,0x7f,0x00,0x00" +} diff --git a/tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_48khz.conf b/tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_48khz.conf new file mode 100644 index 000000000000..dc71c14913cb --- /dev/null +++ b/tools/topology/topology2/include/components/eqiir/highpass_100hz_0db_48khz.conf @@ -0,0 +1,19 @@ +# 100 Hz second order high-pass, gain 0 dB, created with sof_example_iir_eq.m 03-Jun-2024 +Object.Base.data."iir_eq" { + bytes " + 0x53,0x4f,0x46,0x34,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x00,0xa0,0x01,0x03, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x02,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xbd,0x82,0x2c,0xc1, + 0x2e,0xb5,0xd0,0x7e,0x0c,0xcc,0xc7,0x1f, + 0xe9,0x67,0x70,0xc0,0x0c,0xcc,0xc7,0x1f, + 0x00,0x00,0x00,0x00,0xb4,0x7f,0x00,0x00" +} diff --git a/tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_16khz.conf b/tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_16khz.conf new file mode 100644 index 000000000000..fb3d9abf0d6f --- /dev/null +++ b/tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_16khz.conf @@ -0,0 +1,19 @@ +# 100 Hz second order high-pass, gain 20 dB, created with sof_example_iir_eq.m 03-Jun-2024 +Object.Base.data."iir_eq" { + bytes " + 0x53,0x4f,0x46,0x34,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x00,0xa0,0x01,0x03, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x02,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xf5,0x18,0x75,0xc3, + 0x6b,0x52,0x72,0x7c,0x6e,0x92,0x32,0x1f, + 0x24,0xdb,0x9a,0xc1,0x6e,0x92,0x32,0x1f, + 0xfc,0xff,0xff,0xff,0xd0,0x4f,0x00,0x00" +} diff --git a/tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_48khz.conf b/tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_48khz.conf new file mode 100644 index 000000000000..85d70b3e5322 --- /dev/null +++ b/tools/topology/topology2/include/components/eqiir/highpass_100hz_20db_48khz.conf @@ -0,0 +1,19 @@ +# 100 Hz second order high-pass, gain 20 dB, created with sof_example_iir_eq.m 03-Jun-2024 +Object.Base.data."iir_eq" { + bytes " + 0x53,0x4f,0x46,0x34,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x00,0xa0,0x01,0x03, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x58,0x00,0x00,0x00,0x02,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xbd,0x82,0x2c,0xc1, + 0x2e,0xb5,0xd0,0x7e,0x0c,0xcc,0xc7,0x1f, + 0xe9,0x67,0x70,0xc0,0x0c,0xcc,0xc7,0x1f, + 0xfc,0xff,0xff,0xff,0xd1,0x4f,0x00,0x00" +} diff --git a/tools/topology/topology2/include/components/mfcc.conf b/tools/topology/topology2/include/components/mfcc.conf new file mode 100644 index 000000000000..221df8f2d437 --- /dev/null +++ b/tools/topology/topology2/include/components/mfcc.conf @@ -0,0 +1,64 @@ +# +# +# A MFCC component for SOF. All attributes defined herein are namespaced +# by alsatplg to "Object.Widget.mfcc.attribute_name" +# +# Usage: this component can be used by declaring in the parent object. i.e. +# +# Object.Widget.mfcc."N" { +# index 1 +# } +# } + +# +# Where M is pipeline ID and N is a unique integer in the parent object. + +Class.Widget."mfcc" { + # + # Pipeline ID + # + DefineAttribute."index" { + type "integer" + } + + # + # Unique instance for MFCC widget + # + DefineAttribute."instance" { + type "integer" + } + + # Include common widget attributes definition + + + attributes { + !constructor [ + "index" + "instance" + ] + !mandatory [ + "num_input_pins" + "num_output_pins" + "num_input_audio_formats" + "num_output_audio_formats" + ] + + !immutable [ + "uuid" + "type" + ] + !deprecated [ + "preload_count" + ] + unique "instance" + } + + # + # Default attributes for mfcc + # + uuid "73:a7:10:db:a4:1a:ea:4c:a2:1f:2d:57:a5:c9:82:eb" + type "effect" + no_pm "true" + num_input_pins 1 + num_output_pins 1 +} diff --git a/tools/topology/topology2/include/components/mfcc/default.conf b/tools/topology/topology2/include/components/mfcc/default.conf new file mode 100644 index 000000000000..1f9141886de9 --- /dev/null +++ b/tools/topology/topology2/include/components/mfcc/default.conf @@ -0,0 +1,22 @@ +# Exported MFCC configuration 24-Jul-2024 +# cd tools/tune/mfcc; octave setup_mfcc.m +Object.Base.data."mfcc_config" { + bytes " + 0x53,0x4f,0x46,0x34,0x00,0x00,0x00,0x00, + 0x68,0x00,0x00,0x00,0x00,0xa0,0x01,0x03, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x80,0x3e,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0xc3,0x35,0x00,0x2c,0xff,0xff,0x00,0x00, + 0x90,0x01,0xa0,0x00,0x00,0x00,0x14,0x00, + 0x0d,0x00,0x17,0x00,0x00,0x00,0x00,0x64, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00" +} diff --git a/tools/topology/topology2/platform/intel/dmic-default.conf b/tools/topology/topology2/platform/intel/dmic-default.conf index b37521c3b382..61569b42ec80 100644 --- a/tools/topology/topology2/platform/intel/dmic-default.conf +++ b/tools/topology/topology2/platform/intel/dmic-default.conf @@ -21,6 +21,7 @@ Define { DMIC1_NAME dmic16k DMIC0_PCM_CAPS "Passthrough Capture 11" DMIC0_DAI_EQIIR "highpass_40hz_0db" + DMIC1_DAI_EQIIR "highpass_100hz_20db" DMIC1_HOST_PIPELINE_ID 18 DMIC1_DAI_PIPELINE_ID 19 WOV_PIPELINE_ID 20 diff --git a/tools/topology/topology2/platform/intel/dmic-generic.conf b/tools/topology/topology2/platform/intel/dmic-generic.conf index d97f2a417f99..22b811c18c83 100644 --- a/tools/topology/topology2/platform/intel/dmic-generic.conf +++ b/tools/topology/topology2/platform/intel/dmic-generic.conf @@ -729,4 +729,5 @@ Object.PCM.pcm [ IncludeByKey.DMIC1_ENABLE { "passthrough" "platform/intel/dmic1-passthrough.conf" + "mfcc" "platform/intel/dmic1-mfcc.conf" } diff --git a/tools/topology/topology2/platform/intel/dmic1-mfcc.conf b/tools/topology/topology2/platform/intel/dmic1-mfcc.conf new file mode 100644 index 000000000000..e0c394cd7d05 --- /dev/null +++ b/tools/topology/topology2/platform/intel/dmic1-mfcc.conf @@ -0,0 +1,422 @@ + + +Define { + DMIC1_PCM_NAME "DMIC MFCC" +} + +Object.Pipeline.host-gateway-capture [ + { + index $DMIC1_HOST_PIPELINE_ID + core_id $DMIC_CORE_ID + Object.Widget.host-copier.1 { + stream_name $DMIC1_PCM_CAPS + pcm_id $DMIC1_PCM_ID + num_input_audio_formats 1 + num_output_audio_formats 1 + IncludeByKey.NUM_DMICS { + "2" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_bit_depth 16 + in_valid_bit_depth 16 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_bit_depth 16 + out_valid_bit_depth 16 + } + ] + } + "4" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 16 + in_valid_bit_depth 16 + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_channels 4 + out_bit_depth 16 + out_valid_bit_depth 16 + out_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + out_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + } + } + } + Object.Widget.pipeline."1" { + core $DMIC_CORE_ID + } + } +] + +Object.Pipeline.dai-copier-eqiir-gain-module-copier-capture [ + { + index $DMIC1_DAI_PIPELINE_ID + core_id $DMIC_CORE_ID + + Object.Widget.dai-copier.1 { + dai_index 1 + dai_type "DMIC" + copier_type "DMIC" + type dai_out + stream_name $DMIC1_NAME + node_type $DMIC_LINK_INPUT_CLASS + num_input_audio_formats 3 + num_output_audio_formats 1 + IncludeByKey.NUM_DMICS { + "2" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_bit_depth 16 + in_valid_bit_depth 16 + } + { + in_rate $DMIC1_RATE + in_bit_depth 32 + in_valid_bit_depth 24 + in_sample_type $SAMPLE_TYPE_MSB_INTEGER + } + { + in_rate $DMIC1_RATE + in_bit_depth 32 + in_valid_bit_depth 32 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_bit_depth 32 + out_valid_bit_depth 32 + } + ] + } + "4" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 16 + in_valid_bit_depth 16 + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 32 + in_valid_bit_depth 24 + in_sample_type $SAMPLE_TYPE_MSB_INTEGER + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 32 + in_valid_bit_depth 32 + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_channels 4 + out_bit_depth 32 + out_valid_bit_depth 32 + out_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + out_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + } + } + } + + Object.Widget.module-copier."2" { + stream_name $DMIC1_NAME + num_input_audio_formats 1 + num_output_audio_formats 1 + IncludeByKey.NUM_DMICS { + "2" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_bit_depth 32 + in_valid_bit_depth 32 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_bit_depth 16 + out_valid_bit_depth 16 + } + ] + } + "4" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 32 + in_valid_bit_depth 32 + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_channels 4 + out_bit_depth 16 + out_valid_bit_depth 16 + out_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + out_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + } + } + } + + Object.Widget.eqiir.1 { + Object.Control.bytes."1" { + name 'DMIC1 Capture IIR Eq' + IncludeByKey.DMIC1_RATE { + "16000" { + IncludeByKey.DMIC1_DAI_EQIIR { + "passthrough" "include/components/eqiir/passthrough.conf" + "highpass_40hz_0db" "include/components/eqiir/highpass_40hz_0db_16khz.conf" + "highpass_40hz_20db" "include/components/eqiir/highpass_40hz_20db_16khz.conf" + "highpass_100hz_0db" "include/components/eqiir/highpass_100hz_0db_16khz.conf" + "highpass_100hz_20db" "include/components/eqiir/highpass_100hz_20db_16khz.conf" + } + } + "48000" { + IncludeByKey.DMIC1_DAI_EQIIR { + "passthrough" "include/components/eqiir/passthrough.conf" + "highpass_40hz_0db" "include/components/eqiir/highpass_40hz_0db_16khz.conf" + "highpass_40hz_20db" "include/components/eqiir/highpass_40hz_20db_16khz.conf" + "highpass_100hz_0db" "include/components/eqiir/highpass_100hz_0db_16khz.conf" + "highpass_100hz_20db" "include/components/eqiir/highpass_100hz_20db_16khz.conf" + } + } + } + } + num_input_audio_formats 1 + num_output_audio_formats 1 + IncludeByKey.NUM_DMICS { + "2" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_bit_depth 32 + in_valid_bit_depth 32 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_bit_depth 32 + out_valid_bit_depth 32 + } + ] + } + "4" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 32 + in_valid_bit_depth 32 + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_channels 4 + out_bit_depth 32 + out_valid_bit_depth 32 + out_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + out_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + } + } + } + + Object.Widget.gain.1 { + curve_duration 500000 + num_input_audio_formats 2 + num_output_audio_formats 2 + num_input_audio_formats 1 + num_output_audio_formats 1 + IncludeByKey.NUM_DMICS { + "2" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_bit_depth 32 + in_valid_bit_depth 32 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_bit_depth 32 + out_valid_bit_depth 32 + } + ] + } + "4" { + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 32 + in_valid_bit_depth 32 + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_channels 4 + out_bit_depth 32 + out_valid_bit_depth 32 + out_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + out_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + } + } + Object.Control.mixer.1 { + name 'Dmic1 Capture Volume' + } + Object.Control.mixer.2 { + name 'Dmic1 Capture Switch' + + mute_led_use 1 + mute_led_direction 1 + } + } + + + Object.Widget.pipeline."1" { + core $DMIC_CORE_ID + priority $DMIC_PIPELINE_PRIORITY + } + } +] + +Object.Widget.mfcc.1 { + index $DMIC1_HOST_PIPELINE_ID + Object.Control { + bytes."1" { + name 'Analog Capture TDFB bytes' + IncludeByKey.DMIC1_MFCC_PARAMS { + "default" "include/components/mfcc/default.conf" + } + } + } + IncludeByKey.NUM_DMICS { + "2" { + num_input_audio_formats 1 + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_bit_depth 16 + in_valid_bit_depth 16 + } + ] + num_output_audio_formats 1 + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_bit_depth 16 + out_valid_bit_depth 16 + } + ] + } + "4" { + num_input_audio_formats 1 + Object.Base.input_audio_format [ + { + in_rate $DMIC1_RATE + in_channels 4 + in_bit_depth 16 + in_valid_bit_depth 16 + in_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + in_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + num_output_audio_formats 1 + Object.Base.output_audio_format [ + { + out_rate $DMIC1_RATE + out_channels 4 + out_bit_depth 16 + out_valid_bit_depth 16 + out_ch_cfg $CHANNEL_CONFIG_3_POINT_1 + out_ch_map $CHANNEL_MAP_3_POINT_1 + } + ] + } + } +} + +Object.Base.route [ + { + source "dai-copier.DMIC.$DMIC1_NAME.capture" + sink "eqiir.$DMIC1_DAI_PIPELINE_ID.1" + } + { + source module-copier.$DMIC1_DAI_PIPELINE_ID.2 + sink mfcc.$DMIC1_HOST_PIPELINE_ID.1 + } + { + source "mfcc.$DMIC1_HOST_PIPELINE_ID.1" + sink "host-copier.$DMIC1_PCM_ID.capture" + } +] + +Object.PCM.pcm [ + { + name "$DMIC1_PCM_NAME" + id $DMIC1_PCM_ID + direction "capture" + Object.Base.fe_dai.1 { + name "$DMIC1_PCM_NAME" + } + + Object.PCM.pcm_caps.1 { + name $DMIC1_PCM_CAPS + # only 16-bit capture supported now + formats 'S16_LE' + channels_min $NUM_DMICS + channels_max $NUM_DMICS + IncludeByKey.DMIC1_RATE { + "16000" { + rates '16000' + } + "48000" { + rates '48000' + } + } + } + } +] From 1e62f6d2b8e55ce8e3d66800e7a61ba615dacdf2 Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Wed, 24 Jul 2024 15:17:48 +0300 Subject: [PATCH 4/6] Tools: Tune: MFCC: Add export of default blob for tplg2 This patch updates the setup_mfcc.m Octave script to produce configuration blob for topology version 2 builds. Signed-off-by: Seppo Ingalsuo --- tools/tune/mfcc/setup_mfcc.m | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/tools/tune/mfcc/setup_mfcc.m b/tools/tune/mfcc/setup_mfcc.m index 1418dd1f2654..9a1d02335b93 100644 --- a/tools/tune/mfcc/setup_mfcc.m +++ b/tools/tune/mfcc/setup_mfcc.m @@ -45,9 +45,22 @@ function setup_mfcc(cfg) cfg.top_db = 200; % Set to 80 for librosa end +cfg.tplg_fn = '../../topology/topology1/m4/mfcc/mfcc_config.m4'; +cfg.tplg_ver = 1; +cfg.ipc_ver = 3; +export_mfcc_setup(cfg); + +cfg.tplg_fn = '../../topology/topology2/include/components/mfcc/default.conf'; +cfg.tplg_ver = 2; +cfg.ipc_ver = 4; +export_mfcc_setup(cfg); + +end + +function export_mfcc_setup(cfg) + %% Use blob tool from EQ -addpath('../eq'); -fn = '../../topology/topology1/m4/mfcc/mfcc_config.m4'; +addpath('../common'); %% Blob size, size plus reserved(8) + current parameters nbytes_data = 104; @@ -57,7 +70,7 @@ function setup_mfcc(cfg) sh16 = [0 -8]; %% Get ABI information -[abi_bytes, nbytes_abi] = eq_get_abi(nbytes_data); +[abi_bytes, nbytes_abi] = get_abi(nbytes_data, cfg.ipc_ver); %% Initialize correct size uint8 array nbytes = nbytes_abi + nbytes_data; @@ -105,7 +118,20 @@ function setup_mfcc(cfg) v = cfg.use_energy; [b8, j] = add_w8b(v, b8, j); % bool %% Export -eq_tplg_write(fn, b8, 'DEF_MFCC_PRIV', 'Exported MFCC configuration'); +switch cfg.tplg_ver + case 1 + tplg_write(cfg.tplg_fn, b8, "DEF_MFCC_PRIV", ... + "Exported with script setup_mfcc.m", ... + "cd tools/tune/mfcc; octave setup_mfcc.m"); + case 2 + tplg2_write(cfg.tplg_fn, b8, "mfcc_config", ... + "Exported MFCC configuration", ... + "cd tools/tune/mfcc; octave setup_mfcc.m"); + otherwise + error("Illegal cfg.tplg_ver, use 1 for topology v1 or 2 topology v2."); +end + +rmpath('../common'); end From 1deaad3a79bae63149b28505711d6f0cc85ce8ff Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Tue, 20 Aug 2024 18:59:14 +0300 Subject: [PATCH 5/6] Tools: Tune: MFCC: Fix channels handling in audio feature plotter In test topologies the MFCC data can be packed to 1, 2, or 4 channels stream. This change fixes the shown time scale for audio features 3D plot. Signed-off-by: Seppo Ingalsuo --- tools/tune/mfcc/decode_ceps.m | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/tools/tune/mfcc/decode_ceps.m b/tools/tune/mfcc/decode_ceps.m index f98da3052d67..a63677fa3731 100644 --- a/tools/tune/mfcc/decode_ceps.m +++ b/tools/tune/mfcc/decode_ceps.m @@ -1,8 +1,9 @@ -% [ceps, t, n] = decode_ceps(fn, num_ceps) +% [ceps, t, n] = decode_ceps(fn, num_ceps, num_channels) % % Input % fn - File with MFCC data in .raw or .wav format % num_ceps - number of cepstral coefficients per frame +% num_channels - needed for .raw format, omit for .wav % % Outputs % ceps - cepstral coefficients @@ -12,10 +13,10 @@ % SPDX-License-Identifier: BSD-3-Clause % Copyright(c) 2022 Intel Corporation. All rights reserved. -function [ceps, t, n] = decode_ceps(fn, num_ceps, channels) +function [ceps, t, n] = decode_ceps(fn, num_ceps, num_channels) if nargin < 3 - channels = 1; + num_channels = 1; end % MFCC stream @@ -24,7 +25,7 @@ magic = [25443 28006]; % ASCII 'mfcc' as int16 % Load output data -data = get_file(fn); +[data, num_channels] = get_file(fn, num_channels); idx1 = find(data == magic(1)); idx = []; @@ -40,7 +41,7 @@ period_ceps = idx(2)-idx(1); num_frames = length(idx); -t_ceps = period_ceps / channels / fs; +t_ceps = period_ceps / num_channels / fs; t = (0:num_frames -1) * t_ceps; n = 1:num_ceps; @@ -62,7 +63,7 @@ end -function data = get_file(fn) +function [data, num_channels] = get_file(fn, num_channels) [~, ~, ext] = fileparts(fn); @@ -78,10 +79,11 @@ error('Only 16-bit wav file format is supported'); end s = size(tmp); - if s(2) > 1 + num_channels = s(2); + if num_channels > 1 data = int16(zeros(prod(s), 1)); - for i = 1:s(2) - data(i:s(2):end) = tmp(:, i); + for i = 1:num_channels + data(i:num_channels:end) = tmp(:, i); end end otherwise From 8243c8e621f0ec9eabd1c98a87334ece6ecccb35 Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Tue, 13 Aug 2024 18:25:01 +0300 Subject: [PATCH 6/6] App: Boards: Temporarily always set MFCC kconfig to yes To see draft CI build results, will be removed later for proposal. Signed-off-by: Seppo Ingalsuo --- app/boards/intel_adsp_ace15_mtpm.conf | 1 + app/boards/intel_adsp_cavs25.conf | 1 + app/boards/intel_adsp_cavs25_tgph.conf | 1 + 3 files changed, 3 insertions(+) diff --git a/app/boards/intel_adsp_ace15_mtpm.conf b/app/boards/intel_adsp_ace15_mtpm.conf index e4e4b5c872f4..293ffe747e82 100644 --- a/app/boards/intel_adsp_ace15_mtpm.conf +++ b/app/boards/intel_adsp_ace15_mtpm.conf @@ -8,6 +8,7 @@ CONFIG_COMP_SRC_LITE=y CONFIG_COMP_DRC=m CONFIG_COMP_CROSSOVER=y CONFIG_COMP_MULTIBAND_DRC=y +CONFIG_COMP_MFCC=y # power settings CONFIG_PM=y diff --git a/app/boards/intel_adsp_cavs25.conf b/app/boards/intel_adsp_cavs25.conf index ddf70ba9aa85..41c86b31b60a 100644 --- a/app/boards/intel_adsp_cavs25.conf +++ b/app/boards/intel_adsp_cavs25.conf @@ -32,6 +32,7 @@ CONFIG_COMP_DRC=y CONFIG_COMP_CROSSOVER=y CONFIG_COMP_MULTIBAND_DRC=y CONFIG_COMP_ARIA=y +CONFIG_COMP_MFCC=y # route SOF logs to Zephyr logging subsystem CONFIG_SOF_LOG_LEVEL_INF=y diff --git a/app/boards/intel_adsp_cavs25_tgph.conf b/app/boards/intel_adsp_cavs25_tgph.conf index 58855d28183a..71406b9e2b3f 100644 --- a/app/boards/intel_adsp_cavs25_tgph.conf +++ b/app/boards/intel_adsp_cavs25_tgph.conf @@ -31,6 +31,7 @@ CONFIG_COMP_DRC=y CONFIG_COMP_CROSSOVER=y CONFIG_COMP_MULTIBAND_DRC=y CONFIG_COMP_ARIA=y +CONFIG_COMP_MFCC=y # route SOF logs to Zephyr logging subsystem CONFIG_SOF_LOG_LEVEL_INF=y